(a) Field of the Invention
The invention relates to a charge pump, and particularly to a charge pump with power management.
(b) Description of the Related Art
Please refer to FIG. 1, FIG. 1 shows a charge pump based phase-locked loop (PLL) including phase frequency detector (PFD), charge pump (CP), low pass filter (LPF), voltage controlled oscillator (VCO) and divider. In general, the output clock Fout of PLL has jitter caused by the charge sharing effect of the charge pump under the condition of stable supply voltage and low noise interference. Due to the charge sharing effect occur in the charge pump, spikes will be formed at the input terminal of the VCO and after high frequency spikes pass through the low pass filter (LPF), it makes voltage fluctuation at the control input terminal of the VCO. Thus, the output frequency of the VCO is affected by input control voltage, which cause jitter at the output signal.
Charge pump includes current sources and switches. The charge sharing effect is illustrated in FIG. 2. The output of phase/frequency detector (PFD) controls the charge pump so as to increase or decrease the input voltage of the VCO. For example, in the case of the PMOS current source 202 shown in the FIG. 2, the charge sharing effect occurs when the switch 204 of the charge pump is turned off. On the other hands, there is a parasitic capacitor at the output node Vbp of the current pump and the voltage of this parasitic capacitor will be slowly charged up until power supply voltage Vdd. Therefore, when the next control signal UP turns on the switch 204, there will be an extra charge transferred into the output Vc via the switch 204. This is because that the extra charge is charged into the parasitic capacitor at the time when the switch is turned off. This extra charge causes the control voltage Vc of the VCO over the expected voltage. Thereby, it causes the phase/frequency output to exceed the expectation range. The unexpected exceeding value will be adjusted back to normal after few cycles. However, when making next adjustment, the charge sharing due to the NMOS current source 208 and switch will make the adjustment of the VCO become too low. Repeating the above-described process causes the output phase of the PLL to be up and down repeatedly and thereby causes the jitter at the output Vc.
In the relevant arts, one way to reduce the PLL output jitter is to add a charge sharing removal circuit in the charge pump as shown in FIG. 3. In order to remove the charge sharing effect, an operation amplifier or output trans-conductance amplifier (OTA) 302 is added in the charge pump. The operation amplifier or output trans-conductance amplifier 302 receives the VCO control voltage Vc and outputs a voltage Vc′ having the same voltage level as the Vc. When the charge pump switch 304 is turned off (UP=0), another inverse signal will turn on the other complementary switch 306 so that the voltage Vbp remains almost the same with the voltage Vc. Therefore, the charge sharing effect is reduced. This approach can effectively reduce the PLL output jitter, but needs additional power consumption for the OTA circuit.
Furthermore, in order to reduce the PLL output jitter, the method shown in FIG. 4 can be used to reduce the influence of charge sharing. When the switches 402 and 404 are turned off, the other complementary switches 406 and 408 are turned on so that the voltages Vbp′ and Vbn′ will be maintained at a reference voltage. The method in FIG. 4 consumes less power than that in FIG. 3, but the PLL has a larger jitter. No matter which method in FIG. 3 or FIG. 4 is used to design the PLL, it will consume more electric power than the PLL designed by using the traditional charge pump in FIG. 2. That is to say that the PLL structural consideration is a trade-off between power consumption and jitter.